In the art of synthesizing signals, three distinguishable techniques have been used: direct synthesis, indirect synthesis, and numerical synthesis.
In the technique of direct synthesis, the desired signal is produced directly from an oscillator. This technique, however, is limited in frequency. And in synthesizing a wide frequency range, this technique becomes extremely complex and costly. Hence this technique is not widely used for either high frequencies or wide frequency ranges.
In indirect synthesis, phase lock loops with programmable frequency dividers are commonly used to synthesize the desired frequencies. This technique is by far the most widely used at present both in commercial products and in dedicated applications. The method owes its popularity in large part to the advent of inexpensive programmable frequency dividers in integrated circuit form. The result has been a substantial reduction in complexity, especially in comparison with direct synthesis.
However, neither the direct synthesis nor the indirect synthesis technique in the prior art allows for phase-continuous switching of the carrier signal when the desired synthesizer signal is modulated. Furthermore, both techniques require extensive analog components which are subject to drift and malfunction through aging, temperature effects, and the like.
Numerical synthesis with digital techniques is useful for avoiding the above problems. Basically, numerical synthesis consists of generating a stream of points representing a desired signal by using digital logic circuits. Then this numerical data stream is converted into the actual desired signal by means of a digital-to-analog converter (DAC). An example of such a system for synthesizing signals in the prior art is described in U.S. Pat. No. 3,928,813. FIG. 1 shows a block diagram of a typical digital numerical synthesizer known in the art. Therein, the defining relationship for frequency is F=(.DELTA..phi./.DELTA.T)/(2.pi.). If .DELTA.T is the period of the digital clock, then .DELTA..phi. uniquely defines the frequency.
Although prior art synthesizers using the numerical synthesis technique result in less complicated synthesizers than those using the direct and indirect synthesizer techniques, these prior art numerical synthesizers nevertheless have a definite drawback: they characteristically have a low output frequency. The numerical synthesizer in accordance with the present invention overcomes this drawback and simultaneously preserves the other advantages of the numerical synthesis technique.
In order to gain a better understanding of the advantages of the preferred embodiment in accordance with the invention, a brief discussion of numerical synthesizers in the prior art follows.
Essential to any numerical synthesizers is a phase accumulator, as shown in FIG. 1. Its function is to generate a linearly increasing digital signal whose value represents phase in radians. The defining relation between frequency and phase is EQU F=(.DELTA..phi./.DELTA.T)/(2.pi.),
where .DELTA..phi. is a selected value representing a phase increment and .DELTA.T is the period of the system clock for determining an output frequency. The number of different frequencies available in this synthesizer is then 2.sup.M, where M is the number of bits in the field for .DELTA..phi.. If M equals 24 and the clock frequency F.sub.c =1/T is 33.55 MHz, then the frequency resolution is (33.55.times.10.sup.6)/(2.sup.24)=2 Hz. As illustrated in FIG. 1, phase accumulation occurs by repeatedly adding at every clock cycle of 1/T the last phase output to .DELTA..phi.. The phase output, then, at clock cycle N is EQU .phi.out=N.DELTA..phi..
Eventually the adder 10 in the accumulator will overflow, since it is a modulo device with a modulo of 2.sup.M. This overflow does not cause a loss of useful phase, however. Since 2.sup.M represents 2.pi. radians, any phase overflow represents the phase of the next cycle of output. This is illustrated in FIG. 2. The simplicity of the accumulator is obvious. Its disadvantage, however, is in speed. With a 33.55 MHz clock, a new phase is available every 30 nanoseconds. Hence, all M bits must be added and latched within this time. This adding time, then, acts as a speed limitation to the numerical synthesizer. In other words, this places an upper limit on the maximum useful output frequency available.
Once the phase is available, the next step is to convert it to a sinusoidal wave, that is, a wave whose amplitude varies with time. The amplitude is still maintained in digital form. According to the Nyquist or uniform sampling theory, two points on the sine wave are sufficient to perfectly describe it. If the sample points are not exactly correct in phase and amplitude, then harmonics and spurious signals result. The ideal phase-to-amplitude converter (PAC) is a sine lookup table, such as a read-only-memory device (ROM) with 2.sup.M words, having each word or sine amplitude value infinitely accurate. In reality, however, only something less than the ideal is available.
If the constraint of infinite amplitude accuracy is reduced to an accuracy of K bits per word, then the ROM size would be K2.sup.M bits. For example, with M=24 and K=12, the ROM would have 16.7 million words of 12 bits each. Choosing K=12 would give an amplitude resolution of 0.024 percent. This ROM is far too large to be practical, and some bits must be ignored. If some significant bits, say L bits, are tapped off the phase accumulator output, then the phase input to the PAC is truncated. This truncation then results in spurious signals in the system. However, if L=13, then the spurious signals are less than -70 dB. Thus, a practical approach is to use a ROM with 12 bits per word and 8K words.
The size of the ROM lookup table can be reduced even more by partitioning each output cycle into quadrants. Only 0.degree.-90.degree. must now be stored in the ROM. The other quadrants are easily generated from the quadrant number and 0.degree.-90.degree. sine information. This allows the ROM to be 12.times.2K (25K bits) in size. Although this is a reasonable size, it must have a read access time of at least 30 nanoseconds. This access time is very small for this size of ROM.
A useful frequency output for a signal synthesizer is 215 MHz. Since a sampling rate of 2.5 samples per output cycle rather than a mere 2 samples per output cycle would be desirable to compensate for losses, e.g., filter loss, the clock rate corresponding to this sampling rate of 215 MHz would be 215.times.2.5 MHz, or 537 MHz. Constructing a digital system with a sine lookup table having an output of 215 MHz and a clock frequency of 537 MHz is extremely difficult with the prior art. The technique in accordance with the invention, however, allows both a 215 MHz output and a computing rate, or effective clock rate, of 33.55 MHz. This slower rate is much more tractable than a clock rate of 537 MHz. In other words, the novel technique allows high frequency synthesis with the straight-forwardness and advantages of low frequency synthesis.